The present invention relates to the transfer of information over a bus, and more particularly, to arbitration methods and apparatus for arbitrating for use of the bus among a plurality of masters and slaves coupled to the bus.
In personal computers, the utilization of an input/output (I/O) bus can be a limiting factor if this bus is not properly designed and implemented. Certain I/O buses, such as the industry standard architecture (ISA) bus, are adequate for single-user personal computers that do not require extensive video and direct access storage device (DASD) access. With the advent of multi-tasking operating systems and multi-processor (MP) hardware, however, the video and DASD subsystems take up the available I/O bus and memory subsystem bandwidths. This can severely limit the performance of the system as a whole. The attempts to solve this problem involve the use of new and faster I/O buses, such as the Microchannel and the EISA buses. Although partially successful, the demand for even faster buses has become apparent. These faster buses have been necessitated by the faster I/O devices (bus masters) that have become available. The previous buses became overwhelmed, especially in workstations and servers, where multiple masters (such as DASD, LAN, video adapters) commonly reside on the same I/O bus.
The personal computer industry has recently defined a bus standard known as the peripheral component interface (PCI) bus in an attempt to meet the current needs for a faster I/O bus. The PCI bus is well known and the specification of this bus is herein expressly incorporated by reference.
The PCI bus is a general purpose, standard bus, with high throughput. As currently specified, the PCI bus has a theoretical potential of transferring of up to 264 MB/sec. However, this performance is usually never attained since the slave device (typically memory) cannot access or store data at this high rate. Most memory subsystems are limited to a 40-80 MB/sec data transfer rate. The slave device is then forced to insert wait states between the address and data phases of the transfer. This can easily cut the actual bandwidth to 1/2 or 1/4 of the theoretical maximum bandwidth. It is therefore desirable to increase the usable bandwidth of the PCI bus towards its theoretical maximum.
In typical computer systems, there are commonly three phases to a data transfer:
(1) the arbitration phase; PA1 (2) the address/command phase (hereinafter the "address phase"); and PA1 (3) the actual data transfer phase. PA1 (1) address arbitration phase; PA1 (2) address/command phase; PA1 (3) data arbitration phase; and PA1 (4) data transfer phase.
The PCI bus is a "connected transaction bus" which is defined as a bus for which a data phase always immediately follows an address phase (wait states are not considered). In other words, the address phase and data phase are connected such that the data transferred during a data phase is always associated with the address placed on the bus immediately preceding the data phase. The PCI bus allows arbitration phases to overlap with the address and data phases, but does not allow address and data phases to overlap, nor does it allow data phases to occur out of order with respect to the address phase.
By contrast, a bus known as a "split transaction bus" typically has four phases to a data transfer:
In a split transaction bus the data phase does not have to immediately follow the associated address phase placed on the bus. It is not necessary that the data phases occur in the same order that the corresponding address phases occur. Therefore, it is possible for a master to execute multiple address phases before any data is returned. It is also possible to overlap a second master's address phase with a first master's data phase. The address arbitration in a split transaction bus is similar to that of a connected transaction bus. One difference, however, is that on the address phase, the master asserts an address/command signal and a transaction identification (ID) and then immediately releases the address bus. The master may then either wait until the slave returns the data or re-arbitrate for the address bus and execute additional address phases. The slave stores the address/command and the master identification issued during the address phase and then arbitrates for the data bus when it is ready to complete the transfer. When the slave is granted the data bus, it places the transaction ID on the bus at the same time it places the data on the data bus. The master then recognizes its transaction ID and will accept the data, thereby completing the transaction.
In contrast to a split transaction bus, a conventional PCI bus does not use a master that immediately releases the address bus upon the assertion of address/command and identification. Instead, on a conventional PCI bus, the signaling by a slave that it is not ready to complete the transaction causes a retry of the master (a "back-off/retry" feature). This causes the PCI master to re-arbitrate immediately in order to retry the transaction again. The master will normally keep requesting the bus and re-trying the same transaction until the slave is ready, making it more difficult for other masters to use the bus. This reduces the usable bandwidth of the PCI bus.